Modeling and Multi-Objective Optimization of 2.5D Inductor-Based Fully Integrated Voltage Regulators for Microprocessor Applications

This work presents the modeling and the multi-objective optimization of a 2.5D inductor-based Fully Integrated Voltage Regulator (FIVR) with respect to efficiency  and/or chip area power density, i.e. based on the... [ view full abstract ]

This work presents the modeling and the multi-objective optimization of a 2.5D inductor-based Fully Integrated Voltage Regulator (FIVR) with respect to efficiency  and/or chip area power density, i.e. based on the alfa-rho-Pareto front, for microprocessor applications. The Voltage Regulator (VR) consists of a four-phase interleaved buck converter operated in Continuous Conduction Mode (CCM). The rated power of the considered converter is 1W, and input and output voltages are constant and equal to Vin=1.7 V and Vout=0.85 V. The optimization employs analytical models for the switches, manufactured in a 32nm CMOS SOI process, and for the passive components, for racetrack inductors with magnetic core material and deep-trench capacitors fabricated in a silicon interposer. The optimization procedure considers thermal aspects and disregards solutions that lead to excessive temperature rises. According to the optimization results, either high efficiencies, greater than 90%, or high area power densities, with chip power densities greater than 20 W/mm2 and interposer power densities higher then 1.5 W/mm2 are achievable. The optimized design point, selected from the alpha-rho-Pareto-front, features an efficiency of 90.1%, interposer power density of 0.351 W/mm2, and a chip power density of 28.4 W/mm2.