Session: VL1 
 			VLSI, ASIC and FPGAs for signal processing		
	
				
            Chair
             Dr Jim Harkin, Ulster University
		
		 
		
        Time
        
        	11:30 - 12:50 on
            Wednesday, 22nd of June 2016		
		
	 
			
		
								
			
							- 
					
						
							11:30						
						
							
							
								Bo Yang (University College Cork), Satish Grandhi (University College Cork), Christian Spagnol (University College Cork), Sorin Cotofana (TU Delft), Emanuel Popovici (University College Cork)							
						 
					 
				 
							- 
					
						
							12:00						
						
							
							
								Fangzhou Wu (National University of Ireland Maynooth), Rudi Villing (National University of Ireland Maynooth)							
						 
					 
				 
							- 
					
						
							12:30						
						
							
							
								Lei Wan (Guangxi Normal University), Yuling Luo (Guangxi Normal University), Shuxiang Song (Guangxi Normal University), Jim Harkin (University of Ulster), Junxiu Liu (University of Ulster)