Analysis of Ge/GaAs heterojunction-based PN junction tunneling field-effect transistor with dual-metal-gate structure for high-performance and low-power applications

Tunneling field-effect transistors (TFETs) have been studied as a prospective low-power (LP) device because TFETs can achieve a low off-state current (Ioff) and a small subthreshold swing (S) under 60 mV/dec by using the... [ view full abstract ]

Tunneling field-effect transistors (TFETs) have been studied as a prospective low-power (LP) device because TFETs can achieve a low off-state current (I_off) and a small subthreshold swing (S) under 60 mV/dec by using the band-to-band tunneling (BTBT) mechanism. However, a low on-state current (I_on) is caused by the BTBT mechanism. And, I_on and LP performance of TFETs is degraded by the graded doping profile. To reduce of a high tunneling resistance and the impact of the doping profile on tunneling current, it is essential to design a novel device structure. In this paper, a Ge/GaAs heterojunction-based PN junction TFET with a dual-metal-gate structure have been proposed for application of high-performance (HP) and LP device. And, we executed a design optimization for a source-side gate length (L_S-Gate) in the dual-metal-gate structure to improve LP performance as well as I_on. Figure 1 shows schematics of the proposed device. The proposed device is composed of a nanowire structure based on Ge/GaAs heterojunction. A radius (R) in nanowire structure is 10 nm. Doping concentrations of Ge and GaAs layers are p⁺ 5×10¹⁹ cm^-3 and n⁺ 5×10¹⁸ cm^-3, respectively. A total gate length (L_G) is 50 nm and the gate dielectric is used as a high-k dielectric HfO₂ with a thickness (T_ox) of 3 nm. We carried out a simulation work to investigate the performance of the proposed TFET. To obtain an accurate simulation result, various physical models such as Shorkley-Read-Hall (SRH) recombination, trap-assisted tunneling (TAT), BTBT, and concentration-dependent mobility models are used in device simulation. Figure 2 shows transfer characteristics of the proposed TFET with different L_S-Gate. The I_on and S of the dual-metal-gate TFET is largely influenced by a change in the L_S-Gate in the dual-metal-gate. We confirmed that the proposed TFET with a L_S-Gate of 10 nm exhibited a higher I_on of 275.6 μA/μm and a smaller S of 25.4 mV/dec owing to effective tunneling operation. Consequentially, by applying the steep PN junction and dual-metal-gate structure, the proposed TFET simultaneously achieved superior a high I_on and LP performance.