An Electronic Synapse Based on Self-Heating-Enhanced Charge-Trapping in High-k Gate Dielectrics

We present a solution to highly compact plastic synapses in large-scale neuromorphic systems by exploiting the self-heating-enhanced charge-trapping in high-k gate dielectrics of advanced-node transistors. It was shown that... [ view full abstract ]

We present a solution to highly compact plastic synapses in large-scale neuromorphic systems by exploiting the self-heating-enhanced charge-trapping in high-k gate dielectrics of advanced-node transistors. It was shown that the threshold voltage modulation induced by the charge-trapping is larger and more stable with a higher drain bias and hence higher temperature. Taking advantage of this phenomenon, we demonstrate that, by applying appropriately designed voltages to the charge-trapping transistor, it shows the spike timing-dependent plasticity, and the weight change is nonvolatile because of the stable charge-trapping. The conductance of the synapse can be tuned over more than two orders of magnitude and the trade-off between operation speed and accuracy needs to be carefully considered. When used in a system, the proposed synapse only occupies an area of three transistors and does not introduce any extra material or process complexity. The results in this paper pave the way to an ultralow-power and highly integrated self-adaptive neuromorphic system.