Processor-in-Memory Support for Artificial Neural Networks
Abstract
Hardware acceleration of artificial neural network (ANN) processing has potential for supporting applications benefiting from real time and low power operation, such as autonomous vehicles, robotics, recognition and data... [ view full abstract ]
Hardware acceleration of artificial neural network (ANN) processing has potential for supporting applications benefiting from real time and low power operation, such as autonomous vehicles, robotics, recognition and data mining. Most interest in ANNs targets acceleration of deep multi-layered ANNs that can require days of offline training to converge on a desired network behavior. Interest has grown in ANNs capable of supporting unsupervised training, where networks can learn new information from unlabeled data dynamically without the need for offline training. These ANNs require large memories with bandwidths much higher than supported in modern GPGPUs. Custom hardware acceleration and memory co-design holds the potential to provide real-time performance in cases where the performance requirements cannot be met by modern GPGPUs. This work presents a custom processor solution to accelerate two hetero-associative memories (Sparsey and HTM) capable of unsupervised and one-hot learning. This custom processor is implemented as an expandable ASIP built upon a configurable SIMD engine for exploiting parallelism. Functional specialization is implemented utilizing processor-in-memory techniques, which results in up to a 20X speedup and a 2000X reduction in energy per frame compared to a software implementation operating on a dataset for recognition of human actions.
Authors
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Joshua Schabel
(North Carolina State University)
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Lee Baker
(North Carolina State University)
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Sumon Dey
(North Carolina State University)
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Weifu Li
(North Carolina State University)
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Paul Franzon
(North Carolina State University)
Topic Areas
Topics: Neuromorphic, or “brain inspired”, computing , Topics: In-memory processing
Session
OS-03A » Extending CMOS and In-Memory Processing (15:30 - Monday, 17th October, Del Mar Ballroom C)
Paper
ID081_ICRC2016_final.pdf
Presentation Files
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