A simple highly parallel interconnect scheme for ultra-large computing systems to reduce communication power by over a factor of 1000

In this paper we compare the energy efficiency obtained from dedicated low frequency highly parallel communication channels in large scale computing systems implemented using simple wires with conventional high data-rate... [ view full abstract ]

In this paper we compare the energy efficiency obtained from dedicated low frequency highly parallel communication channels in large scale computing systems implemented using simple wires with conventional high data-rate serialized transmission line type channels. Advances in technology such as 3D integration, interposers and Si Interconnect Fabrics make dense short interconnects feasible, offering new possibilities for ultra-large computing systems, by overcoming the limited I/O constraints of conventional packages and boards. Without contributing to the functionality of the system, chip-to-chip communication represents an increasing energy and area cost as the computing system scales up. The relationship of power and interconnect density in large complex computing systems is also explored in this paper. We show that the advanced CHIPS Interconnect Fabric which we are developing, can be integrated with the wafer scale integration schemes to eliminate the traditional packaging and the SerDes for chip-to-chip communication, and consequently reduce the communication power by 103X to 105X depending on the type of the system with a concomitant boost in interconnect density by at least 100X. These improvements are scalable with system size and are independent of technology node and device specifics. This opens the opportunity for complex distributed computing systems including brain-inspired computing systems.