Computationally-Redundant Energy-Efficiency Processing for Y'all (CREEPY)
Abstract
Dennard scaling has ended. Lowering the voltage supply (Vdd) to sub volt levels causes intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable as a means to lower the power required by a... [ view full abstract ]
Dennard scaling has ended. Lowering the voltage supply (Vdd) to sub volt levels causes intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable as a means to lower the power required by a processor core. However, if it were possible to recover the occasional losses due to lower Vdd in an efficient manner, one can effectively lower power. In other words, by deploying the right amount and kind of redundancy, we can strike a balance between overhead incurred in achieving reliability and savings realized in permitting lower Vdd. One promising approach is the Redundant Residual Number System (RRNS) representation.
RRNS has the important property of being closed under addition, subtraction and multiplication, thus enabling error correction of errors caused due to both faulty storage and compute units. Furthermore, the incorporated approach uses a fraction of the overhead and is more efficient when compared to the conventional technique used for compute-reliability.
In this article, we provide an overview of the CREEPY core and discussions of other aspects of the RRNS problems in CREEPY, including error detection/correction, overflow detection and signed number representation. Finally, we demonstrate the usability of such a computer by quantifying a performance-reliability trade-off.
Authors
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Bobin Deng
(Georgia Institute of Technology)
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Sriseshan Srikanth
(Georgia Institute of Technology)
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Eric Hein
(Georgia Institute of Technology)
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Paul Rabbat
(Georgia Institute of Technology)
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Thomas Conte
(Georgia Institute of Technology)
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Erik DeBenedictis
(Sandia National Laboratories)
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Jeanine Cook
(Sandia National Laboratories)
Topic Areas
Topics: Error-tolerant logic and circuits , Topics: Extending Moore’s law and augmenting CMOS
Session
OS-06A » Error Tolerant Logic and Circuits (15:30 - Tuesday, 18th October, Del Mar Ballroom C)
Paper
ID015_ICRC2016_final.pdf
Presentation Files
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