Accelerating Image Algorithm Development using Soft Co-Processors on FPGAs

FPGAs can offer high performance with low power and low hardware usage. However, with current software, FPGAs are hard to program, and lengthy re-synthesis times make them unsuitable for the algorithm experimentation which is... [ view full abstract ]

FPGAs can offer high performance with low power and low hardware usage. However, with current software, FPGAs are hard to program, and lengthy re-synthesis times make them unsuitable for the algorithm experimentation which is typical of developing image processing applications. In this paper, we present a system model based on a set of Soft Co-Processors, each of which implements a basic image-level operation (or a common combination of such operations) based on the high-level operators in Image Algebra. Both ‘debug’ (generic but unoptimised) and ‘release’(specific and optimised) versions of the Soft Co-Processors can be used. The advantage of debug mode is that no re-synthesis is required during algorithm experimentation. For release mode, a novel macro-based transformation tool enables the creation of a set of reusable HLS skeleton co-processors which require the user only to write a C function to obtain a new, special-purpose Soft Co-Processor.

Initial experiments with several algorithms show that the area and speed overheads for using debug (rather than release) mode are both around 25-30%, thus enabling algorithm development to take place on the FPGA itself.  For creating function-specific Co-processors using our macro-based tool, the overheads compared with an expert hardware design are around 20%.